CAREER: Energy-Efficient and Energy-Proportional Silicon-Photonic Manycore Architectures

Funding Agency: National Science Foundation

Directorate: Computer & Information Science & Engineering (CISE)

Division: Computer and Communication Foundations (CCF)

Program: Software and Hardware Foundations (SHF)

Award Number: 1453853

Program Manager: Sankar Basu

PIs: Nikos Hardavellas (Northwestern University)

Institutions: Department of Computer Science and Department of Electrical and Computer Engineering, Northwestern University

Affiliated Graduate Students: Ali Murat Gok, Haiyang (Drake) Han, Vijay Kandiah, Georgios Tziantzioulis, Gaurav Chaudhary, Ujjwal Kotaru

Project Dates: May 1, 2015 to April 30, 2021

Abstract:

Increasing energy demands have put computing on an unsustainable technological, economic and environmental path. Unfortunately, a large fraction of this energy is wasted, with data transfers being one of the major contributors to energy consumption. At the same time, while the demand for computing grows, modern microprocessors are increasingly constrained by physical limitations, which prevent them from realizing their full potential. Area, power, thermal, off-chip bandwidth, and yield limitations constrain single-chip designs to a relatively small number of cores, beyond which scaling becomes impractical. Multi-chip designs can overcome these limitations, but require a cross-chip interconnect with bandwidth, latency, and energy efficiency characteristics well beyond the reach of conventional electrical signaling. The introduction of nano-photonic interconnects, as undertaken in this proposal, can meet these requirements and allow systems to break free of the limitations of single-chip designs.

Within the context of this research, a rigorous educational plan is also integrated into the research agenda that strongly connects research to education, and enhances the participation of minorities and undergraduates in research. This project capitalizes on existing collaborations with the Searle Center for Teaching Excellence at Northwestern University to implement innovative educational approaches, Northwestern's Science in Society outreach initiatives for the general public, and Northwestern's Office of STEM Education Partnerships to develop K-12 STEM outreach activities with outreach potential extending to 140+ schools in the Chicago metropolitan area, reaching 368 teachers and 30,000 students.

Specific technical aspects of this research aims to develop scalable, energy-efficient, and energy-proportional interconnects for future multicores. To achieve this vision, the research seeks to understand and mitigate the energy inefficiencies of the dominant power consumers in silicon-photonics. The project involves a cross-cutting approach to combine developments in novel materials, emerging devices, and 3D-stacking with research in architectural and micro-architectural techniques, memory systems, the runtime environment, and the operating system, to develop adaptive techniques that minimize the energy consumed by nano-photonic interconnects without sacrificing their performance. The overall effort culminates on the design of a virtual macro-chip, a disaggregated many-core design supported by a silicon-photonic interconnect that reaches scales of thousands of cores, at a performance and power level impossible to realize with conventional technology.

Project Page: http://paragon.cs.northwestern.edu/projects/energy_proportional_photonics/

Journals and Juried Conference Papers:

1. Haiyang Han, Theoni Alexoudi, Chris Vagionas, Nikos Pleros and Nikos Hardavellas. Pho$: A Case for Shared Optical Cache Hierarchies. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2021 (Nominated for Best Paper Award)

2. Vijay Kandiah, Scott Peverelle, Mahmoud Khairy, Junrui Pan, Amogh Manjunath, Timothy G. Rogers, Tor M. Aamodt and Nikos Hardavellas. AccelWattch: A Power Modeling Framework for Modern GPUs. In Proceedings of the 54th IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece, October 2021

3. Vijay Kandiah, Ali Murat Gok, Georgios Tziantzioulis and Nikos Hardavellas. ST² GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative Adders. In Proceedings of the Design Automation Conference (DAC), San Francisco, CA, December 2021

4. Enrico A. Deiana, Vincent St-Amour, Peter Dinda, Nikos Hardavellas and Simone Campanoni. Unconventional Parallelization of Nondeterministic Applications. In Proceedings of the 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Williamsburg, VA, March 2018

5. Yigit Demir and Nikos Hardavellas. Techniques for Energy Proportionality in Optical Interconnects. Photonic Interconnects for Computing Systems, G. Nicolescu, S. Le Beux, M. Nikdast and J. Xu (Eds.), The River Publishers' Series in Optics and Photonics, River Publishers, 2017

6. Enrico A. Deiana, Vincent St-Amour, Peter Dinda, Nikos Hardavellas and Simone Campanoni. POSTER: The Liberation Day of Nondeterministic Programs. In Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), Portland, OR, September 2017

7. Yigit Demir, Nikos Terzenidis, Haiyang Han, Dimitris Syrivelis, George T. Kanellos, Nikos Hardavellas, Nikos Pleros, Srikanth Kandula and Fabian Bustamante. Harnessing Path Diversity for Laser Control in Data Center Optical Networks. In Proceedings of the 2017 IEEE Photonics Society Summer Topical Meeting Series (IEEE SUM), Optical Switching Technologies for Datacom and Computercom Applications (OSDC), San Juan, Puerto Rico, July 2017 (Invited Paper)

8. Ali Murat Gok and Nikos Hardavellas. VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder. In Proceedings of the 27th ACM Great Lakes Symposium on VLSI (GLSVLSI), Banff, Alberta, Canada, May 2017

9. Y. Demir and N. Hardavellas. Energy-Proportional Photonic Interconnects. In ACM Transactions on Architecture and Code Optimization (ACM TACO), Vol. 13(5), December 2016

10. Y. Demir and N. Hardavellas. SLaC: Stage Laser Control for a Flattened Butterfly Network. In Proceedings of the 22nd IEEE International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, March 2016

11. G. Tziantzioulis, A. M. Gok, S M Faisal, N. Hardavellas, S. Ogrenci-Memik, and S. Parthasarathy. Lazy Pipelines: Enhancing Quality in Approximate Computing. In Proceedings of the Design, Automation, and Test in Europe (DATE), Dresden, Germany, March 2016

12. Y. Demir and N. Hardavellas. Towards Energy-Proportional Optical Interconnects. In Proceedings of the 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS), Dresden, Germany, March 2016 (Invited Paper)

13. S M Faisal, G. Tziantzioulis, A. M. Gok, S. Parthasarathy, N. Hardavellas, and S. Ogrenci-Memik. Edge Importance Identification for Energy Efficient Graph Processing. In Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData), Santa Clara, CA, October 2015

14. B. Patel, G. Memik and N. Hardavellas. SCP: Synergistic Cache Compression and Prefetching. In Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD), New York City, NY, October 2015

15. Y. Demir and N. Hardavellas. Parka: Thermally Insulated Nanophotonic Interconnects. In Proceedings of the 9th International Symposium on Networks-on-Chip (NOCS), Vancouver, Canada, September 2015

16. Y. Demir and N. Hardavellas. Towards Energy-Efficient Photonic Interconnects. In Proceedings of SPIE, Optical Interconnects XV, San Francisco, CA, February 2015. Also selected to appear in 2015 SPIE Green Photonics Program, SPIE Photonics West (published prior to this award)

17. Y. Demir and N. Hardavellas. LaC: Integrating Laser Control in a Photonic Interconnect. In Proceedings of the IEEE Photonics Conference (IPC), pp. 28-29, La Jolla, CA, October 2014 (published prior to this award)

18. Y. Demir and N. Hardavellas. EcoLaser: An Adaptive Laser Control for Energy-Efficient On-Chip Photonic Interconnects. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, La Jolla, CA, August 2014 (published prior to this award)

19. Y. Demir, Y. Pan, S. Song, N. Hardavellas, G. Memik and J. Kim. Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects. In Proceedings of the ACM International Conference on Supercomputing (ICS), pp. 303-312, Munich, Germany, June 2014 (published prior to this award)

Other Invited Presentations / Publications:

20. Nikos Hardavellas. Energy-Proportional Photonic Interconnects: From the Chip to the Datacenter. IBM Research, T. J. Watson Research Center, Yorktown Heights, NY, USA, December 2018

21. Yigit Demir and Nikos Hardavellas. Energy-Proportional Photonic Interconnects. In 12th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Stockholm, Sweden, January 2017

22. Haiyang Han, Yigit Demir, Nikos Hardavellas, Fabian Bustamante and Srikanth Kandula. Energy-Proportional Photonic Networks with Stage Laser Control. 5th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2016

23. Georgios Tziantzioulis, Ali Murat Gok, S M Faisal, Nikos Hardavellas, Seda Ogrenci-Memik and Srinivasan Parthasarathy. Lazy Pipelines: Enhancing Quality in Approximate Computing. 5th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2016

24. Yigit Demir, Nikos Hardavellas. Towards Energy Proportional Nanophotonic Interconnects. 4th Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2015

25. Y. Demir and N. Hardavellas. EcoLaser: An Adaptive Laser Control for Energy-Efficient On-Chip Photonic Interconnects. 3rd Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2014 (published prior to this award)

26. Y. Demir, Y. Pan, S. Song, N. Hardavellas, G. Memik and J. Kim. Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects. 3rd Greater Chicago Area Systems Research Workshop (GCASR), Chicago, IL, April 2014 (published prior to this award)

27. Y. Demir and N. Hardavellas. Galaxy: Pushing the Power and Bandwidth Walls with Optically Connected Disintegrated Processors. 2nd Greater Chicago Area Systems Research Workshop (GCASR), Evanston, IL, April 2013 (published prior to this award)

28. Y. Pan, Y. Demir, N. Hardavellas, J. Kim, and G. Memik. Exploring Benefits and Designs of Optically Connected Disintegrated Processor Architecture. Workshop on the Interaction between Nanophotonic Devices and Systems (WINDS), co-located with the 43rd International Symposium on Microarchitecture (MICRO), Atlanta, GA, 2010 (published prior to this award)

Other Publications:

29. Gaurav Chaudhary. A Simulator for Distributed Quantum Computing. MS Thesis, Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL, 2020; Technical Report NU-CS-2020-15, Department of Computer Science, Northwestern University, Evanston, IL, 2020

30. Yigit Demir. High Performance and Energy Efficient Computer System Design Using Photonic Interconnects. PhD Thesis, Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, 2015 (Best Ph.D. Dissertation Award in Computer Engineering)

31. Y. Demir and N. Hardavellas. LaC: Integrating Laser Control in a Photonic Interconnect. Technical Report NU-EECS-14-03, Northwestern University, Evanston, IL, April 2014 (published prior to this award)

32. Y. Demir and N. Hardavellas. EcoLaser: An Adaptive Laser Control for Energy Efficient On-Chip Photonic Interconnects. Technical Report NU-EECS-14-02, Northwestern University, Evanston, IL, April 2014 (published prior to this award)

33. Y. Demir, Y. Pan, S. Song, N. Hardavellas, J. Kim, and G. Memik. Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects. Technical Report NU-EECS-13-08, Northwestern University, Evanston, IL, July 2013 (published prior to this award)

K12 Outreach:

1. How to Design a Microprocessor
Lesson plan materials and Windows/Mac application available at
http://paragon.cs.northwestern.edu/#K12

The goal of this lesson is for 11th-12th grade students to learn some basic concepts in processor architecture. Using a simple graphical user interface of a parameterized processor model from recent computer architecture research, the students can run simple experiments in which they can modify the architectural parameters of a microprocessor and estimate their impact on performance, area, power, and off-chip data rates. These estimates, in turn, shed light on the tradeoffs that arise in microprocessor design, and guide the students to an optimal design that conforms to the physical constraints.
The lesson addresses NGSS standards in Science and Engineering Practices (SEP), Disciplinary Core Ideas (DCI) HS-ETS1-2, 3, 4, Cross Cutting Concepts (CCC).

Artifacts:

1. AccelWattch, a microbenchmark-based quadratic programming framework for the power modeling of GPUs, and an accurate power model for NVIDIA Quadro Volta GV100.

- Zenodo DOI for AccelWattch MICRO-2021 artifact

- GitHub link for AccelWattch sources and framework

- GitHub link for AccelWattch microbenchmarks and validation benchmarks

Disclaimer: This material is based upon work supported by the National Science Foundation under Grant Number CCF-1453853. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.